Search - fft ip

[Other resource] FFT变换的IP核的源代码 VHDL~

Description: FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
Platform: | Size: 32421 | Author: 陈旭 | Hits:

[matlab] fft

Description: This example describes a 32K-point fast Fourier transform (FFT) using the Altera FFT IP MegaCore.
Platform: | Size: 983863 | Author: joey196t@yahoo.com.tw | Hits:

Description: 程序算任意点FFT和小波变换,以及可选择多种小波及小波变换后的单频带重够,另算信号的Lipschitz指数,高级数字信号处理!-counting procedures arbitrary point FFT and Wavelet Transform, and the choice of multiple wavelet and the wavelet transform of a single-band heavy enough, and another count signal Lipschitz index advanced digital signal processing!
Platform: | Size: 3072 | Author: Sword | Hits:

[ARM-PowerPC-ColdFire-MIPS] FFT_IP

Description: Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
Platform: | Size: 419840 | Author: zxinkai | Hits:

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

Description: xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
Platform: | Size: 1432576 | Author: ningchang | Hits:

[VHDL-FPGA-Verilog] 2C35F672_FFT

Description: 在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
Platform: | Size: 474112 | Author: lovenevol | Hits:

[VHDL-FPGA-Verilog] fft_IPcore

Description: 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
Platform: | Size: 8719360 | Author: 李杰 | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[VHDL-FPGA-Verilog] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[Speech/Voice recognition/combine] C3DSound

Description: 这是个3D环绕声的程序，主要是频谱分析和一些时域的幅值和相位的变换，fft，等核心做。-This is a 3D surround sound procedures, mainly spectrum analyzer and some time-domain amplitude and phase of the transform, fft, so the core.
Platform: | Size: 51200 | Author: | Hits:

[Algorithm] FFT

Description: 快速傅利叶变换 C 语言源代码，可以很好移植到不同的系统-Fast Fourier Transform C language source code, can be ported to different systems
Platform: | Size: 16384 | Author: quinn yang | Hits:

[VHDL-FPGA-Verilog] FFT_ip_veriolg_code

Description: ip核的FFTverilog源代码，说明不是很具体-ip nuclear FFTverilog source code, that is not very specific
Platform: | Size: 34816 | Author: james_chan | Hits:

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

Description: This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
Platform: | Size: 456704 | Author: alex | Hits:

[Speech/Voice recognition/combine] fft

Description: Special Requirements ?nx must be a power of 2. ?The index array must be set up by bitrev_index before the function DSP_bitrev_cplx is called. ?If nx ?4K, one can use the char (8-bit) data type for the "index" variable. This would require changing the LDH when loading index values in the assembly routine to LDB. This would further reduce the size of the Index Table by half its size.
Platform: | Size: 1024 | Author: pranav | Hits:

[SCM] Quartus

Description: Quartus中fft ip core的使用.txt-Fft ip core in Quartus use. Txt
Platform: | Size: 3072 | Author: ziyaajlm | Hits:

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[Other resource] FFT变换的IP核的源代码 VHDL~

[matlab] fft

[Algorithm] rwdrcoef

[ARM-PowerPC-ColdFire-MIPS] FFT_IP

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

[VHDL-FPGA-Verilog] 2C35F672_FFT

[VHDL-FPGA-Verilog] fft_IPcore

[VHDL-FPGA-Verilog] ip_fft128

[VHDL-FPGA-Verilog] fftinterface

[Speech/Voice recognition/combine] C3DSound

[Algorithm] FFT

[VHDL-FPGA-Verilog] FFT_ip_veriolg_code

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

[Speech/Voice recognition/combine] fft

[SCM] Quartus

[VHDL-FPGA-Verilog] FFT_verilog

[VHDL-FPGA-Verilog] fftip

[Other] 121114100FFT-IP

[Speech/Voice recognition/combine] test

[VHDL-FPGA-Verilog] Altera FFT IP核使用实例

CodeBus www.codebus.net

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

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[Other resource] FFT变换的IP核的源代码 VHDL~

[matlab] fft

[Algorithm] rwdrcoef

[ARM-PowerPC-ColdFire-MIPS] FFT_IP

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

[VHDL-FPGA-Verilog] 2C35F672_FFT

[VHDL-FPGA-Verilog] fft_IPcore

[VHDL-FPGA-Verilog] ip_fft128

[VHDL-FPGA-Verilog] fftinterface

[Speech/Voice recognition/combine] C3DSound

[Algorithm] FFT

[VHDL-FPGA-Verilog] FFT_ip_veriolg_code

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

[Speech/Voice recognition/combine] fft

[SCM] Quartus

[VHDL-FPGA-Verilog] FFT_verilog

[VHDL-FPGA-Verilog] fftip

[Other] 121114100FFT-IP

[Speech/Voice recognition/combine] test

[VHDL-FPGA-Verilog] Altera FFT IP核 使用实例

CodeBus www.codebus.net

[VHDL-FPGA-Verilog] Altera FFT IP核使用实例